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| (R) SP8121 Monolithic, 12-Bit Data Acquisition System s Complete Monolithic 8-Channel, 12-Bit DAS s 100kHz Throughput s 16-Bit Microprocessor Bus Interface s Parallel 12-Bit Output s Latched MUX Address s Tri-State Latched Output s No Missing Codes to 12-Bits s 32-pin SOIC and PDIP Available s 200mW Power Dissipation Maximum * Formerly part of the SP410 Series. DESCRIPTION The SP8121 is a complete data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V unipolar full scale inputs. Output data is formatted in 12-bit parallel. The SP8121 is available in 32-pin plastic DIP or SOIC packages, operating over the commercial temperature range. MULTIPLEXER 12-BIT A/D CONVERTER MUX DECODE REFERENCE CONTROL LOGIC CLOCK SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System 1 TRI-STATE LATCH (c) Copyright 2000 Sipex Corporation ABSOLUTE MAXIMUM RATINGS VCC to Common Ground .............................................. 0V to +16.5V VLOGIC to Common Ground ............................................... 0V to +7V Analog Common to Digital Common Ground ............... -0.5V to +1V Digital Inputs to Common Ground .................... -0.5V to VLOGIC+0.5V Digital Outputs to Common Ground ................. -0.5V to V LOGIC+0.5V Multiplexer Analog Inputs ...................................... -16.5V to +31.5V Gain and Offset Adjustment ................................ -0.5V to VCC+0.5V Analog Input Maximum Current ........................................... 100mA Temperature with Bias Applied ............................. -55C to +125C Storage Temperature ............................................ -65C to +150C Lead Temperature, Soldering .................................... 300C, 10sec CAUTION: ESD (ElectroStatic Discharge) sensitive device. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Personnel should be properly grounded prior to handling this device. The protective foam should be discharged to the destination socket before devices are removed. SPECIFICATIONS (TA= 25C and nominal supply voltages unless otherwise noted) MIN. ANALOG INPUTS Input Voltage Range Multiplexer Inputs Configuration Input Impedance ON Channel OFF Channel Input Bias Current/Channel Crosstalk OFF to ON Channel TYP. 0 to +5 MAX. UNIT V CONDITIONS 8 Single-ended 109 1010 +10 +250 -90 -80 -70 nA nA dB dB dB Bits LSB LSB LSB LSB LSB %FSR Parallel with 30pF Parallel with 5pF 25C -55C to +125C 10kHz, 0V to +5VPk-to-pk 50kHz, 0V to +5VPk-to-pk 100kHz, 0V to +5VPk-to-pk ACCURACY Resolution 12 Linearity Error -K +0.5 -J +1 Differential Non-Linearity -K +1 -J +2 +0.5 +4 Offset Error Gain Error +0.3 +1 No Missing Codes -K Guaranteed TRANSFER CHARACTERISTICS Throughput Rate 100 MUX Settling/Acquisition 1.9 A/D Conversion 8.1 STABILITY +0.5 +2.5 Linearity Offset +5 +25 Gain +10 +50 DIGITAL INPUTS Capacitance 5 Logic Levels VIH +2.4 +5.5 VIL -0.5 +0.8 IIH +5 IIL +5 Adjustable to zero Adjustable to zero kHz s s ppm/C ppm/C ppm/C pF V V A A SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 2 SPECIFICATIONS (continued) (TA= 25C and nominal supply voltages unless otherwise noted) MIN. TYP. MAX. DIGITAL OUTPUTS Capacitance 5 Logic Levels +2.4 VOH VOL +0.4 Leakage Current 40 Data Output Positive true binary POWER REQUIREMENTS VLOGIC +4.5 +5.5 ILOGIC 0.8 4 VCC +11.4 +16.5 ICC 9 12 Power Dissipation 140 200 ENVIRONMENTAL AND MECHANICAL Operating Temperature Commercial (-J, -K) 0 +70 Storage Temperature -65 +150 Packages -_P 32-pin Plastic DIP -_S 32-pin SOIC UNIT pF V V A CONDITIONS IOH 500A IOL 1.6mA High impedance, data bits only V mA V mA mW C C SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 3 SP8121 PINOUT DB11 (MSB) SP8121 CONTROL TRUTH TABLE CE DB0 (LSB) LATCH R/C 0 0 H ->L 1 OPERATION Start Conversion Start Conversion Start Conversion Enable 12-bit Output (when STATUS=0) L->H 1 1 S DB10 MA2 MA1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 MA0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 CLOCK REF 12-BIT ADC DECODE 8-CHANNEL MULTIPLEXER 5 6 7 8 9 10 11 12 13 14 15 16 1 CONTROL LOGIC 1 2 3 4 SP8121 MULTIPLEXER TRUTH TABLE LATCH MA2 H -> L H -> L H -> L H -> L H -> L 0 0 0 0 1 1 1 1 X X MA1 0 0 1 1 0 0 1 1 X X MA0 0 1 0 1 0 1 0 1 X X OPERATION CHO Selected CH1 Selected CH2 Selected CH3 Selected CH4 Selected CH5 Selected CH6 Selected CH7 Selected Prev. CH "n" Held Prev. CH "n" Held OFFSET ADJ. ANA. IN. CH0 ANA. IN. CH1 ANA. IN. CH2 ANA. IN. CH3 ANA. IN. CH4 ANA. IN. CH5 ANA. IN. CH6 SP8121 PINOUT STATUS -- Identifies valid data output; goes to logic high during conversion; goes to logic low when conversion is completed and data is valid R/C -- Read/Convert -- Initiates conversion on the high-to-low transition; logic low disconnects data bus; logic high initiates read CE -- Chip Enable -- Logic low disables read or convert; logic high enables read or convert LATCH -- MUX Address Latch -- Logic high to low transition captures MUX address on MUX address lines MA0, MA1, MA2 -- MUX Address 0, 1 & 2 -- Selects analog input channels CH0 through CH7 DB0 through DB11 -- Data Outputs -- Logic high is binary true; logic low binary false ANA. IN. CH7 GAIN ADJ. ANA. GND. STATUS CE VLOGIC VCC R/C H -> L H -> L H -> L 0 1 SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 4 FEATURES The SP8121 is a complete data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V unipolar full scale inputs. Output data is formatted in 12-bit parallel. Linearity errors of +0.5 and +1.0 LSB, and Differential Non-linearity to 12-bits is guaranteed, with no missing codes over temperature. Channel-to-channel crosstalk is typically -85dB. Multiplexer settling plus acquisition time is 1.9s maximum; A/D conversion time is 8.1s maximum. The SP8121 is available in a 32-pin plastic DIP or SOIC packages. Operating temperature range is 0C to +70C commercial. The SAR, timed by the clock, sequences through the conversion cycle and returns an end-of-convert flag to the control section of the ADC. The clock is then disabled by the control section, which puts the STATUS output line low. The control section is enabled to allow the data to be read by external command (R/C). MULTIPLEXER CONTROL On the SP8121 the address lines MA0, MA1, and MA2 are latched into the internal address decode circuitry with the falling edge of LATCH. Data set-up time for these inputs is >=50nS. The MUX address data must remain valid for the current conversion for a minimum of 3.0 S after the conversion is initiated. This is the time required for the MUX and Sample and Hold to settle. However it is advisable that the MUX not be changed at all during the full 10S conversion time due to capacitive coupling effects of digital edges through the silicon. The SP8121 multiplexer inputs have been designed to allow substantial overvoltage conditions to occur without any damage. The inputs are diode-clamped and further protected with a 200 series resistor. As a result, momentary (10 seconds) input voltages can be as low as -16.5V or as high as +31.5V with no change or degradation in multiplexer performance or crosstalk. This feature allows the output voltage of an externally connected op amp to swing to +15V supply levels with no multiplexer damage. Complicated power-up sequencing is not required to protect the SP8121. The multiplexer inputs may be damaged, however, if the inputs are allowed to either source or sink greater than 100mA. INITIATING A CONVERSION CIRCUIT OPERATION The SP8121 is a complete 8-channel data acquisition systems (DAS), with on-board multiplexer, voltage reference, sample-and-hold, clock and tri-state outputs. The digital control architecture is very similar to the industry-standard 574-type A/D, and uses identical control lines and digital states. The multiplexer for the SP8121 is identical in operation to many discrete devices available today, except that it has been integrated into the single-chip DAS. The appropriate channel is selected using the MUX address lines MA0, MA1, and MA2 per the truth table. The selected analog input is fed through to the ADC. The input impedance into any MUX channel will be on the order to 109 ohms, since it is connected to the integral sampling structure of the capacitor DAC. Crosstalk is kept to -85dB at 0V to 5Vp-p over an input frequency range of 10kHz to 50kHz. When the control section of the SP8121 initiates a conversion command the internal clock is enabled, and the successive approximation register (SAR) is reset to all zeros. Once the conversion has been started it cannot be stopped or restarted. Data is not available at the output buffers until the conversion has been completed. The SP8121 was designed to require a minimum of control to perform a 12-bit conversion. The control input used are R/C which tri-states the outputs when high and starts the conversion when low, in combination with CE. The last of the control inputs to reach the correct state starts the conversion, therefore either may be dynamically controlled. The nominal delay from each is the same and they may change state simultaneously. In order to ensure that a particular input controls the conversion, the other should be set up at least 50ns earlier. The STATUS line indicates when a conversion is in process and when it is complete. SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 5 +15V +15V 100K 125K SP8121 GAIN ADJUST 7 0.3% Trim Range 19K 10K Center pot for zero correction SP8121 OFFSET ADJUST 6 -1.5mV to +3mV 5K Figure 1. Offset Adjust Figure 2. Gain Adjust The conversion cycle is started when R/C is brought low and must be held low for a minimum of 50ns. The R/C signal will also put the output latches in a tri-state mode when low. Approximately 200ns after R/C is low, STATUS will change from low to high. This output signal will stay high while the SP8121 is performing a conversion. Valid data will be latched to the output bus, through internal control, 500ns prior to the STATUS line transitioning from a high to low. READING THE DATA Please refer to Figure 4. To read data from the SP8121, the R/C and CE control lines are used. R/C must be high a minimum of 50ns prior to reading the data to allow time for the output latches to come out of the high impedance tri-state mode. CE is used to access the data. The first 8 MSBs will be on pins 32 through 25, with pin 32 being the MSB. The remaining 4 LSBs will be on pins 21 through 24 with pin 21 being the LSB. When CE is switched from one state to the next, there is a 50ns output latch propagation delay between the MSBs and LSBs being present on the output pins. CALIBRATION The calibration procedure for the SP8121 consists of adjusting the most negative input voltage (0V) to the ideal output code for offset adjustment, and then adjusting the most positive input voltage (5.0V) to its ideal output code for gain adjustment. Offset Adjustment The offset adjustment must be completed first. Please refer to Figure 1. Apply an input voltage of 0.5LSB or 610V to any multiplexer input. Adjust the offset potentiometer so that the output code fluctuates evenly between 000...000 and 000...001. It is only necessary to observe the lower eight LSB's during this procedure. Gain Adjustment With the offset adjusted, the gain error can now be trimmed to zero. (Please refer to Figure 2.) The ideal input voltage corresponding to 1.5 LSB's below the nominal full scale input value, or +4.988V, is applied to any multiplexer input. The gain potentiometer is adjusted so that the output code alternates evenly between 111...111 and 111...110. Again, only the lower eight LSB's need be observed during this procedure. With the above adjustment made, the converter is now calibrated. SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 6 CE tSRC R/C tHEC tHRC STATUS tDSC DB11 - DB0 HIGH IMPEDANCE tC CONVERT MODE DYNAMIC CHARACTERISTICS VCC = +15V; VLOGIC = +5V; TA = 25C PARAMETER tHEC CE Pulse Width tSRC R/C to CE Setup tHRC R/C Low during CE High tDSC Status Delay from CE Figure 3. Convert Mode Timing MIN. 50 50 50 200 TYP. MAX. UNIT ns ns ns ns CONDITIONS CE tSRR R/C tHRR STATUS tHD DB11 - DB0 HIGH IMPEDANCE tDD READ MODE DYNAMIC CHARACTERISTICS VCC = +15V; VLOGIC = +5V; TA = 25C PARAMETER tSRR R/C to CE Setup tHRR R/C High after CE Low tHD tDD Data Valid after CE Low Access Time from CE MIN. 0 0 25 150 150 TYP. 0 50 MAX. UNIT ns ns ns ns ns CONDITIONS DATA VALID tHL tHL Output Float Delay Figure 4. Read Mode Timing SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 7 R/C tHRH tDS STATUS tDDR DB11 - DB0 HIGH-Z tHDR DATA VALID tC HIGH-Z HIGH PULSE FOR R/C DYNAMIC CHARACTERISTICS VCC = +15V; VLOGIC = +5V; TA = 25C PARAMETER tHRH High R/C Pulse Width tDS tC STATUS Delay from R/C Conversion Time 13 MIN. 25 200 25 150 25 TYP. MAX. UNIT ns ns s ns ns TMIN to TMAX CONDITIONS tDDR Data Access Time tHDR Data Valid after R/C Low Figure 5. High Pulse for R/C -- Outputs Enabled While R/C is High, Otherwise High Impedance tMDH tMDS MA0 - MA2 tHRL R/C tDS STATUS tHDR DB11 - DB0 DATA VALID tC tHS DATA VALID LOW PULSE FOR R/C DYNAMIC CHARACTERISTICS VCC = +15V; VLOGIC = +5V; TA = 25C PARAMETER tHRL Low R/C Pulse Width tDS tHS Status Delay from R/C 25 tHDR Data Valid after R/C tMDS MUX Data Setup tMDH MUX Data Valid Figure 6. Low Pulse for R/C MIN. 50 200 TYP. MAX. UNIT ns ns ns ns ns 10 s CONDITIONS Status Delay after Data Valid 500 50 3 SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 8 Figure 7. FFT; 6kHz, 5V (0dB) Full Scale Input; FS = 100kHz Figure 8. FFT; 12kHz, 5V (0dB) Full Scale Input; FS = 100kHz Figure 9. FFT; 24kHz, 5V (0dB) Full Scale Input; FS = 100kHz Figure 10. FFT; 48kHz, 5V (0dB) Full Scale Input; FS = 100kHz Figure 11. FFT; 48kHz, 1V (-14dB) Input; FS = 100kHz SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 9 +1 LSB INLE -1. LSB +1. LSB DNLE -1. LSB 0 2048 4095 Figure 12. Non-Linearity SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 10 PACKAGE: PLASTIC DUAL-IN-LINE (WIDE) E1 E D1 = 0.005" min. (0.127 min.) D A1 = 0.015" min. (0.381min.) A = 0.25" max. (6.350 max). A2 C O eA = 0.600 BSC (15.240 BSC) L e = 0.100 BSC (2.540 BSC) B1 B DIMENSIONS (Inches) Minimum/Maximum (mm) A2 B B1 C D E E1 L O 32-PIN 0.125/0.195 (3.175/4.953) 0.014/0.022 (0.366/0.559 0.030/0.070 (0.762/1.778) 0.008/0.015 (0.203/0.381) 1.645/1.655 (41.78/42.04) 0.600/0.625 (15.24/15.87) 0.485/0.580 (12.31/14.73) 0.115/0.200 (2.921/5.080) 0/ 15 (0/15) SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 11 PACKAGE: PLASTIC SMALL OUTLINE (SOIC) E H D A O e B A1 L DIMENSIONS (Inches) Minimum/Maximum (mm) A A1 B D E e H L O 32-PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.810/0.822 (20.57/20.88) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8) SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 12 ORDERING INFORMATION 12-Bit Data Acquisition System with 12-Bit Parallel Data Output and latched MUX Address Inputs: Commercial Temperature Range (0C to +70C) .................................... Linearity ................................................................................ Package SP8121JP ............................................................................................... +1.0LSB INL ...................................................... 32-pin, 0.6" Plastic DIP SP8121KP .............................................................................................. +0.5LSB INL ...................................................... 32-pin, 0.6" Plastic DIP SP8121JS ............................................................................................... +1.0LSB INL ................................................................ 32-pin, 0.3" SOIC SP8121KS .............................................................................................. +0.5LSB INL ................................................................ 32-pin, 0.3" SOIC Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. SP8121DS/02 SP8121 Monolithic, 12-Bit Data Acquisition System (c) Copyright 2000 Sipex Corporation 13 |
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